The Performance of Various Lightweight Block Ciphers FPGA Architectures: A Review

  • Marwa Subhi Ibrahim Computer Engineering Department, Engineering College, Al-Iraqia University /College of Engineering, Diyala University, Diyala, Baquba, Iraq
  • Yasir Amer Abbas College of Engineering, Diyala University, Diyala, Baquba, Iraq
  • Mudhafar Hussein Ali Computer Engineering Department, Engineering College, Al-Iraqia University, Iraq
الكلمات المفتاحية: FPGA, Lightweight, Block Cipher

الملخص

Today most of our devices connected with Internet to assistance us to improve our decisions. The number of people are using wireless and Internet networks increased day by day, which this increased improved the encryption mechanisms for devices and protect user data transfer over an unsecured network. Due to the limited resources for most portable devices, the concept of ubiquitous computing presents must be working terms of security, which contains Confidentiality, Integrity, Authentication, and non-repudiation. In comparison to energy-efficient with cryptography the conventional approaches are expensive and complicated and high-power consumption. The design of lightweight cryptography has solved big number of problem for hardware implementation with the conventional cryptography. In this paper, performance and efficiency depend of architectures review for lightweight block cipher algorithm base of FPGA design and implementation.

المراجع

[1] A. K. Sahu, S. Sharma, and D. Puthal, “Lightweight Multi-party Authentication and Key Agreement Protocol in IoT-based E-Healthcare Service,” ACM Trans. Multimed. Comput. Commun. Appl., vol. 17, no. 2s, pp. 1–20, 2021, doi: 10.1145/3398039.
[2] A. Alamer, B. Soh, A. H. Alahmadi, and D. E. Brumbaugh, “Prototype device with lightweight protocol for secure RFID communication without reliable connectivity,” IEEE Access, vol. 7, pp. 168337–168356, 2019.
[3] B. J. Mohd, T. Hayajneh, and A. V. Vasilakos, “A survey on lightweight block ciphers for low-resource devices: Comparative study and open issues,” J. Netw. Comput. Appl., vol. 58, pp. 73–93, 2015, doi: 10.1016/j.jnca.2015.09.001.
[4] G. Hatzivasilis, K. Fysarakis, I. Papaefstathiou, and C. Manifavas, “A review of lightweight block ciphers,” J. Cryptogr. Eng., vol. 8, no. 2, pp. 141–184, 2018.
[5] Nayancy, S. Dutta, and S. Chakraborty, “A survey on implementation of lightweight block ciphers for resource constraints devices,” J. Discret. Math. Sci. Cryptogr., pp. 1–22, 2020.
[6] P. Panahi, C. Bayılmış, U. Çavuşoğlu, and S. Kaçar, “Performance evaluation of lightweight encryption algorithms for IoT-based applications,” Arab. J. Sci. Eng., vol. 46, no. 4, pp. 4015–4037, 2021.
[7] D. J. Rani and S. E. Roslin, “Light weight cryptographic algorithms for medical internet of things (IoT)-a review,” in 2016 Online international conference on green engineering and technologies (IC-GET), 2016, pp. 1–6.
[8] A. A. Yazdeen, S. R. M. Zeebaree, M. M. Sadeeq, S. F. Kak, O. M. Ahmed, and R. R. Zebari, “FPGA implementations for data encryption and decryption via concurrent and parallel computation: A review,” Qubahan Acad. J., vol. 1, no. 2, pp. 8–16, 2021.
[9] P. Yalla and J.-P. Kaps, “Lightweight cryptography for FPGAs,” in 2009 international conference on reconfigurable computing and FPGAs, 2009, pp. 225–230.
[10] R. Anusha and V. Veena Devi Shastrimath, “LCBC-XTEA: High Throughput Lightweight Cryptographic Block Cipher Model for Low-Cost RFID Systems,” in Advances in Intelligent Systems and Computing, 2019, vol. 986, pp. 185–196. doi: 10.1007/978-3-030-19813-8_20.
[11] M. Sbeiti, M. Silbermann, A. Poschmann, and C. Paar, “Design space exploration of present implementations for FPGAS,” in 2009 5th Southern Conference on Programmable Logic (SPL), 2009, pp. 141–145.
[12] A. Biswas, A. Majumdar, S. Nath, A. Dutta, and K. L. Baishnab, “LRBC: a lightweight block cipher design for resource constrained IoT devices,” J. Ambient Intell. Humaniz. Comput., pp. 1–15, 2020.
[13] M. Al-Shatari, F. A. Hussin, A. A. Aziz, G. Witjaksono, M. S. Rohmad, and X. T. Tran, “An Efficient Implementation of LED Block Cipher on FPGA,” 2019 1st Int. Conf. Intell. Comput. Eng. Towar. Intell. Solut. Dev. Empower. our Soc. ICOICE 2019, pp. 9–13, 2019, doi: 10.1109/ICOICE48418.2019.9035193.
[14] H. Aktaş, “Implementation of GOST 28147-89 encryption and decryption algorithm on FPGA,” 2018.
[15] R. Anusha and V. Veena Devi Shastrimath, “Y. A. Abbas, A. S. Hameed, S. H. Alwan, and M. A. Fadel, ‘Efficient hardware implementation for lightweight mCrypton algorithm using FPGA,’ vol. 23, no. 3, pp. 1674–1680, 2021, doi: 10.11591/ijeecs.v23.i3.pp1674-1680.,” in Computer Science On-line Conference, 2019, pp. 185–196.
[16] C. Kella, Z. Mishra, and B. Acharya, “A Compact & Low Power Architecture of XXTEA192 Lightweight block cipher,” in 2021 6th International Conference on Communication and Electronics Systems (ICCES), 2021, pp. 972–976.
[17] A. A. M. Ragab, A. Madani, A. M. Wahdan, and G. M. I. Selim, “Design, analysis, and implementation of a new lightweight block cipher for protecting IoT smart devices,” J. Ambient Intell. Humaniz. Comput., pp. 1–18, 2021.
[18] H. Zodpe and A. Sapkal, “An efficient AES implementation using FPGA with enhanced security features,” J. King Saud Univ. - Eng. Sci., vol. 32, no. 2, pp. 115–122, 2020, doi: 10.1016/j.jksues.2018.07.002.
[19] N. Wu, Z. A. Ali, M. M. Shaikh, M. R. Yahya, and M. Aamir, “Compact and high speed architectures of KASUMI block cipher,” Wirel. Pers. Commun., vol. 106, no. 4, pp. 1787–1800, 2019.
[20] M. Madani and C. Tanougast, “FPGA implementation of an enhanced chaotic-KASUMI block cipher,” Microprocess. Microsyst., vol. 80, p. 103644, 2021.
[21] P. Pachange and G. Bansod, “A fast and efficient datapath designs of lightweight cipher RoadRunner on FPGA’s for resource constrained environments,” in 2019 Sixth International Conference on Internet of Things: Systems, Management and Security (IOTSMS), 2019, pp. 65–72.
[22] C. A. Lara-Nino, A. Diaz-Perez, and M. Morales-Sandoval, “Lightweight hardware architectures for the present cipher in FPGA,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 64, no. 9, pp. 2544–2555, 2017.
[23] A. Mhaouch, W. Elhamzi, and M. Atri, “Lightweight Hardware Architectures for the Piccolo Block Cipher in FPGA,” 2020 Int. Conf. Adv. Technol. Signal Image Process. ATSIP 2020, pp. 5–8, 2020, doi: 10.1109/ATSIP49331.2020.9231586.
[24] N. H. Yousif, Y. A. Abbas, and M. H. Ali, “Lightweight ANU-II block cipher on field programmable gate array,” Int. J. Electr. Comput. Eng., vol. 12, no. 3, p. 2194, 2022.
[25] P. Singh, B. Acharya, and R. K. Chaurasiya, “High Throughput Architecture for KLEIN Block Cipher in FPGA,” IEMECON 2019 - 9th Annu. Inf. Technol. Electromechanical Eng. Microelectron. Conf., pp. 64–69, 2019, doi: 10.1109/IEMECONX.2019.8877021.
[26] Q. Tang and F. Du, Internet of Things Security: Principles and Practice. Springer, 2021.
[27] S. S. Dhanda, B. Singh, and P. Jindal, “Lightweight cryptography: a solution to secure IoT,” Wirel. Pers. Commun., vol. 112, no. 3, pp. 1947–1980, 2020.
[28] R. A. F. Lustro, A. M. Sison, J. T. Labiano, and R. P. Medina, “A lightweight block cipher implementation in the resource-constrained internet of things,” in Proceedings of 2019 the 9th International Workshop on Computer Science and Engineering, WCSE 2019, International Workshop on Computer Science and Engineering (WCSE), 2020, pp. 776–782.
[29] S. Q. A. Al-Rahman, A. Sagheer, and O. A Dawood, “A Hybrid Lightweight Cipher Algorithm,” Int. J. Comput. Digit. Syst., 2021.
[30] K. Vipin and S. A. Fahmy, “FPGA dynamic and partial reconfiguration: A survey of architectures, methods, and applications,” ACM Comput. Surv., vol. 51, no. 4, pp. 1–39, 2018.
منشور
2022-09-17
القسم
المقالات